// Questions
- Generate a truth table for
- A four input NAND gate
- A four-input NOR gate
- Can a NAND gate be used as an INVERTER? If so, illustrate how with a two-input NAND gate.
- Can a NOR gate be used as an INVERTER? If so, illustrate how with a two-input NOR gate.
- Assuming POSITIVE logic, what do each of the following voltage levels represent (1 or 0)?
- Find the TTL part number and the number of gates per chip for each of the following logic gates:
- Inverters
- Two-input OR gates
- Four-input NAND gates
- Two-input NOR gates
- Two-input AND gates
- What pin numbers must be conected to power supply and ground for each of the following TTL chips:
- Show that the distributive law of OR over AND holds true by means of a truth table, that is show that
- Show that the distributive law of AND over OR holds true by means of a truth table, that is show that
- Use a truth table to prove the absorption rule, that is
- Use a truth table to prove the following theorem
- Given the following TTL gates and connections, give an expression for the output function f
- What would be the result of connecting two inverters in tandem? Why would this be useful thing to do in a digital circuit?
- What is the disadvantage of leaving the inputs of a logic gate unconnected?
// Answers
- Generate a truth table for
- A four input NAND gate
- A four-input NOR gate
| A |
B |
C |
D |
F |
| 0 |
0 |
0 |
0 |
1 |
| 0 |
0 |
0 |
1 |
1 |
| 0 |
0 |
1 |
0 |
1 |
| 0 |
0 |
1 |
1 |
1 |
| 0 |
1 |
0 |
0 |
1 |
| 0 |
1 |
0 |
1 |
1 |
| 0 |
1 |
1 |
0 |
1 |
| 0 |
1 |
1 |
1 |
1 |
| 1 |
0 |
0 |
0 |
1 |
| 1 |
0 |
0 |
1 |
1 |
| 1 |
0 |
1 |
0 |
1 |
| 1 |
0 |
1 |
1 |
1 |
| 1 |
1 |
0 |
0 |
1 |
| 1 |
1 |
0 |
1 |
1 |
| 1 |
1 |
1 |
0 |
1 |
| 1 |
1 |
1 |
1 |
0 |
| A |
B |
C |
D |
F |
| 0 |
0 |
0 |
0 |
1 |
| 0 |
0 |
0 |
1 |
0 |
| 0 |
0 |
1 |
0 |
0 |
| 0 |
0 |
1 |
1 |
0 |
| 0 |
1 |
0 |
0 |
0 |
| 0 |
1 |
0 |
1 |
0 |
| 0 |
1 |
1 |
0 |
0 |
| 0 |
1 |
1 |
1 |
0 |
| 1 |
0 |
0 |
0 |
0 |
| 1 |
0 |
0 |
1 |
0 |
| 1 |
0 |
1 |
0 |
0 |
| 1 |
0 |
1 |
1 |
0 |
| 1 |
1 |
0 |
0 |
0 |
| 1 |
1 |
0 |
1 |
0 |
| 1 |
1 |
1 |
0 |
0 |
| 1 |
1 |
1 |
1 |
0 |
- Can a NAND gate be used as an INVERTER? If so, illustrate how with a two-input NAND gate.
- Can a NOR gate be used as an INVERTER? If so, illustrate how with a two-input NOR gate.
- Assuming POSITIVE logic, what do each of the following voltage levels represent (1 or 0)?
- .3v=0
- 2.4v=1
- 5.0v=1
- 0.0v=0
- 1.9v=undefined
| LOW |
HIGH |
| 0.0-0.8v |
2.0-5.0v |
- Find the TTL part number and the number of gates per chip for each of the following logic gates:
- Inverters 7404 6-inputs-
- Two-input OR gates
- Four-input NAND gates: 7420 2 gates
- Two-input NOR gates: 7402 4 gates
- Two-input AND gates
- What pin numbers must be conected to power supply and ground for each of the following TTL chips:
- 7400
14:Vcc
7:GND
- 7420
14:Vcc
7:GND
- 7476
5:Vcc
13:GND
- 74151
16:Vcc
8:GND
- Show that the distributive law of OR over AND holds true by means of a truth table, that is show that
| X |
Y |
Z |
YZ |
X+Y |
X+Z |
(X+Y)(X+Z) |
X+(YZ) |
| 0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| 0 |
0 |
1 |
0 |
0 |
1 |
0 |
0 |
| 0 |
1 |
0 |
0 |
1 |
0 |
0 |
0 |
| 0 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
| 1 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
| 1 |
0 |
1 |
0 |
1 |
1 |
1 |
1 |
| 1 |
1 |
0 |
0 |
1 |
1 |
1 |
1 |
| 1 |
1 |
1 |
0 |
1 |
1 |
1 |
1 |
- Show that the distributive law of AND over OR holds true by means of a truth table, that is show that
| X |
Y |
Z |
(Y+Z) |
XY |
XZ |
X(Y+Z) |
(XY)+(XZ) |
| 0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| 0 |
0 |
1 |
1 |
0 |
0 |
0 |
0 |
| 0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
| 0 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
| 1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| 1 |
0 |
1 |
1 |
0 |
1 |
1 |
1 |
| 1 |
1 |
0 |
1 |
1 |
0 |
1 |
1 |
| 1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
- Use a truth table to prove the absorption rule, that is
| X |
Y |
(XY) |
X+XY |
| 0 |
0 |
0 |
0 |
| 0 |
1 |
0 |
0 |
| 1 |
0 |
0 |
1 |
| 1 |
1 |
1 |
1 |
- Use a truth table to prove the following theorem
| X |
Y |
(X+Y) |
X(X+Y) |
| 0 |
0 |
0 |
0 |
| 0 |
1 |
1 |
0 |
| 1 |
0 |
1 |
1 |
| 1 |
1 |
1 |
1 |
- Given the following TTL gates and connections, give an expression for the output function f
| A |
B |
1 |
F |
| 0 |
0 |
1 |
1 |
| 0 |
1 |
1 |
1 |
| 1 |
0 |
1 |
1 |
| 1 |
1 |
1 |
0 |
(AB1)'=(AB)'
| A |
B |
1 |
F |
| 0 |
0 |
1 |
0 |
| 0 |
1 |
1 |
0 |
| 1 |
0 |
1 |
0 |
| 1 |
1 |
1 |
0 |
(A+B+1)'=0
- What would be the result of connecting two inverters in tandem? Why would this be useful thing to do in a digital circuit?
It returns the original input. An even number of inverters act like a buffer
- What is the disadvantage of leaving the inputs of a logic gate unconnected?
The unconected gate becomes a 1 and there is a possibility the gate will not work as desired. This is the case for a NOR gate
Unconnected inputs can pick up electrical noise and rapidly change between high and low states in an unpredictable way. This is likely to make the IC behave erratically and it will significantly increase the supply current. To prevent problems all unused inputs should be connected to the supply (either +Vs or 0V), this applies even if that part of the IC is not being used in the circuit!
Unconnected inputs are not a logic
low; they are not predictable and usually (but not always) float to the high input state. Inputs should
always be connected to a gate output, a Logic High (+5V), or a Logic Low (0V or Ground).
Source: Passafine, John and Michael Douglas, Digital Logic Design
